Hitherto, as one of systems of decoding convolution codes, Viterbi decoding system is known. This Viterbi decoding system is the maximum likelihood decoding system with respect to convolution codes, and is adapted to select series nearest to received code series (This series will be called the maximum likelihood path hereinafter) from code series which can be generated from encoder of the transmitting side to thereby carry out error correction.
In the Viterbi decoding apparatus, when data received through transmission path from the transmitting side is inputted, series nearest to received code series (maximum likelihood path) is selected from code series which can be generated from encoder of the transmitting side to generate decode data on the basis of this selected content. Namely, in the Viterbi decoding apparatus, when received data is inputted, branch metric of this received data is calculated by branch metric calculating circuit to deliver this calculated result (branch metric) to ACS (Add Compare Select) circuit. Further, the ACS circuit adds and compares Hamming distance (branch metric) between receive signal and path and state metric of branch metrics until that time with respect to respective two paths caused to flow together to a certain state on the basis of branch metric delivered from the branch metric calculating circuit and state metric (accumulated sum) delivered from state metric memory circuit to select state metric of high likelihood on the basis of this comparison result to deliver this selected content to path memory circuit, and to deliver state metric newly obtained to normalization circuit.
In this case, FIG. 1 is an explanatory view showing an example of transition diagram in the Viterbi decoding. In the case where constraint length is "3", branch metric between receive signal and path and state metric of branch metrics until that time are added and compared with respect to respective two paths caused to flow together to a certain state every respective time slots. Thus, state metric of the high likelihood is selected on the basis of this comparison result.
The normalization circuit normalizes state metric outputted from the ACS circuit to allow it to be value within the range set in advance to deliver it to a state metric memory circuit. The state metric memory circuit stores the normalized state metric delivered from the normalization circuit to feed it back to the ACS circuit. Moreover, the path memory circuit stores selected content outputted from the ACS circuit to deliver it to maximum likelihood decoding judgment circuit. The maximum likelihood decoding judgment circuit judges the maximum likelihood path on the basis of the selected content stored in the path memory circuit to generate decode data to output the decode data thus generated.
In the conventional Viterbi decoding apparatus, there was used a normalization circuit 10 of a configuration as shown in FIG. 2, for example. This normalization circuit 10 is composed of a minimum value calculating circuit 11, and plural subtracting circuits 12. The minimum value calculating circuit 11 is supplied with state metrics corresponding to the number of states. The minimum value calculating circuit 11 calculates minimum value of all state metrics inputted thereto to output the minimum state metric. The respective subtracting circuits 12 subtract the minimum state metric from respective input state metrics to respectively output the subtraction results as normalized state metrics.
Meanwhile, in such a Viterbi decoding apparatus, an approach is employed in the normalization circuit to determine the minimum value from all state metrics sent from the ACS circuit to output the determined minimum value as correction value to subtract this correction value from respective state metrics to thereby carry out normalization thus to obtain normalized state metrics.
In general, in the Viterbi decoding, in order to enhance the error correction ability, constraint length K of code is caused to be large. With respect to the constraint length K of code, the number of states becomes equal to 2.sup.k-1. For this reason, in the normalization circuit, processing for calculating the minimum value from 2.sup.k-1 number of state metrics every time slot is required.
Implementation of time required processing which detects the minimum value from 2.sup.k-1 number of state metrics in the feedback loop returning to the ACS circuit via the normalization circuit and the state metric memory circuit from the ACS circuit lowers operation speed of the entirety of the Viterbi decoding apparatus.
Moreover, since the normalization processing is carried out by subtraction between corresponding state metric and the minimum value of the state metrics, in the case where the constraint length K is caused to be large, 2.sup.k-1 number of subtracting circuits 12 are required in the above-mentioned normalization circuit 10. As a result, the circuit scale is increased.
This invention has been made for the purpose of solving the above-described problems, and its object is to provide a Viterbi decoding apparatus having small circuit scale and capable of carrying out high speed operation. In addition, this invention has been made for the purpose of solving the above-described problems, and its object is to provide a Viterbi decoding method which permits reduction in the circuit scale and high speed operation.